Superconductor switches and systems used in, for example, optical data links, would require multiple superconductor chips with high-speed interconnections of 40–150 Gbps per line. At these bit rates, clock recovery is an important design consideration with respect to the data link onto each superconductor chip and with respect to chip-to-chip connections.
In one type of clock recovery circuit used in superconductors, a clock pulse that travels around a ring oscillator formed from a Josephson transmission line (JTL) loop with a single clock-out tap and a single data-in tap including a one-way buffer, generates a clock pulse train that has a period corresponding to the clock period. The circulating clock pulse splits at the clock-out tap to produce the clock output, and to continue to travel around the JTL loop.
The clock pulse that continues to travel around the JTL loop also splits at the data-in tap, but the resulting data pulse that enters the data-in tap escapes in the one-way buffer. A subsequent data pulse entering the oscillator at the data-in tap splits and propagates around the oscillator loop in both directions. The forward-traveling pulse establishes the new clock pulse with new phase, while the back-traveling pulse annihilates the preexisting clock pulse, thereby enabling almost instantaneous clock recovery.
However, the above clock recovery circuit has certain associated limitations. For example, while the clock phase in the above circuit can be advanced, it cannot be retarded when, for example, an input data pulse is late relative to the pre-existing clock pulse. In addition, data input slightly decreases the clock period due to pulse interaction on the oscillator loop. Also, a newly established clock phase may have an associated error due to interaction between the clock and data pulses. Together, these limitations compromise the accuracy of such a circuit.
Therefore, it is an object of the present invention to provide a clock recovery circuit for a superconductor system that is capable of instantaneously resetting the phase of a system clock regardless of the timing of an input data pulse with respect to the system clock.
It is another object of the present invention to provide a clock recovery circuit for a superconductor system designed for inhibiting pulse interaction and therefore for instantaneously resetting the phase of a system clock with minimal associated timing error.
It is another object of the present invention to provide a clock recovery circuit for a superconductor system having simple and flexible design parameters.